1. Field of Invention
Embodiments of this disclosure generally relate to semiconductor devices and, more particularly, to nonvolatile memory devices having three-dimensional (3-D) structures.
2. Description of Related Art
A nonvolatile memory device retains data stored therein although the supply of power is cut off. As the recent improvement of the degree of integration of 2-D memory devices in which memory cells are formed in a single layer over a silicon substrate reaches the limit, there is proposed a 3-D nonvolatile memory device in which memory cells are vertically stacked on a silicon substrate.
The structure of a known 3-D nonvolatile memory device and problems thereof are described in detail below.
FIGS. 1A and 1C are diagrams illustrating the structure of a known 3-D nonvolatile memory device.
FIG. 1A is a cross-sectional view of the known 3-D nonvolatile memory device, FIG. 1B is a plan view of the known 3-D nonvolatile memory device, and FIG. 1C is a circuit diagram showing the cell array of the known 3-D nonvolatile memory device.
As shown in FIGS. 1A to 1C, the known 3-D nonvolatile memory device includes a plurality of memory cells which are stacked along a plurality of channel layers CH protruded from a substrate SUB.
More particularly, the known 3-D nonvolatile memory device includes a source region SOURCE into which an N type impurity is doped in the substrate SUB. The known 3-D nonvolatile memory device further includes the plurality of channel layers CH protruded from the substrate SUB. The plurality of channel layers CH is arranged in a first direction I-I′ and a second direction II-II′ that crosses the first direction I-I′. The known 3-D nonvolatile memory device further includes a lower select line LSL, a plurality of word lines WL, and an upper select line USL which are stacked along the channel layers CH. In FIG. 1A, reference numeral 11 denotes a gate insulating layer, and 12 denotes a tunnel insulating layer, a memory layer, and a charge blocking layer. Additionally, BL denotes a bit line, and S denotes a source line.
In this structure, a plurality of the memory cells is coupled in series between an upper select gate and a lower select gate, thus forming one string. The strings are vertically arranged from the substrate SUB.
In this structure, the source region SOURCE has high resistance because it is formed by doping an N type impurity into the substrate SUB. Accordingly, there is a problem in that the driving speed of the memory device is slow.